Digital counting circuits are most often implemented using flip-flop circuits connected in propagating daisy chain fashion so that whenever one stage switches from a logical 1 to a logical 0, the next following stage is activated to change state. Another common embodiment for a digital counting circuit is in the form of an adder which adds the amount by which the counter is to be advanced to the current count within the counter.
Neither of these well known counting circuit configurations lend themselves well to implementation using dynamic logic circuits because of the substantial time required within each dynamic logic gate to perform a decision. For this reason, daisy chain flip-flop counters operate at very low speed when implemented in dynamic logic. Although often capable of being operated faster than daisy chain counters, the adder implemented counters described above also are slower than is often desired and require substantially higher numbers of logic decisions circuits and, therefore, occupy much more integrated circuit chip area than is optimally desired.
A third dynamic logic counter known in the art includes a substantially complex steering logic circuit having inputs from all counting stages to allow parallel logical decisions to change the state of the proper counter stages thereby incrementing the counter to the next count. Because all logical decisions are made substantially in parallel and, therefore, substantially during the same time interval, a steering circuit controlled counter requires a very short time to increment. An example of such a third embodiment is U.S. Pat. No. 3,654,441. The steering circuit controlled counter, however, has the serious drawback of requiring complex logic circuits. In addition, counters having a large number of counting stages cannot be built because the maximum number of AND gate inputs or OR gate inputs specified for the dynamic logic circuit family being used, will quickly be exceeded when connecting the dynamic logic circuits to ensure that all logical decisions are made at the same time. The maximum number of inputs which can be connected to a logic circuit are, of course, determined by such considerations as series device impedance, device capacitance and so forth.